Keyword : yield optimization

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
Masako FUJII Koji NII Hiroshi MAKINO Shigeki OHBAYASHI Motoshige IGARASHI Takeshi KAWAMURA Miho YOKOTA Nobuhiro TSUDA Tomoaki YOSHIZAWA Toshikazu TSUTSUI Naohiko TAKESHITA Naofumi MURATA Tomohiro TANAKA Takanari FUJIWARA Kyoko ASAHINA Masakazu OKADA Kazuo TOMITA Masahiko TAKEUCHI Shigehisa YAMAMOTO Hiromitsu SUGIMOTO Hirofumi SHINOHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/08/01
Vol. E91-C  No. 8 ; pp. 1338-1347
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures (ICMTS2007))
Category: 
Keyword: 
large-scale integration, logic circuit fault diagnosis, SRAM, yield optimization, 
 Summary | Full Text:PDF
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7 ; pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization, 
 Summary | Full Text:PDF
A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance
Tomohiro FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3 ; pp. 727-734
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
analog LSI, yield optimization, hierarchical design, constraint generation, Mahalanobis' distance, 
 Summary | Full Text:PDF