Keyword : yield improvement


Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning
Kota MUROI Hayato MASHIKO Yukihide KOHIRA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-A  No. 7 ; pp. 894-903
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
post-silicon delay tuningprogrammable delay elementyield improvementpower consumption reduction
 Summary | Full Text:PDF(1.1MB)

Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology
Toru TANZAWA 
Publication:   
Publication Date: 2018/01/01
Vol. E101-C  No. 1 ; pp. 78-81
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
3D NANDdesign for manufacturabilityenergy efficientyield improvement
 Summary | Full Text:PDF(649.4KB)

Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data
Abderrahim DOUMAR Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1104-1115
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
defect tolerancefault tolerancefield programmable gate array (FPGA)shifting configurations datayield improvement
 Summary | Full Text:PDF(779.1KB)