Keyword : worst-case design

Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment
Yuji KUNITAKE Kazuhiro MIMA Toshinori SATO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 483-491
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
worst-case designtiming errorco-simulationparameter variation
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