Keyword : worst design

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
Akira KOTABE Kiyoo ITOH Riichiro TAKEMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 555-563
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
0.5-V 25-nm 6-T SRAM cellboosted word voltageFD-MOSFETsrepairworst design
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