Keyword : wire length


Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation
Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2795-2798
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
low power designwire lengthfloorplanbit sliceone-hot code
 Summary | Full Text:PDF

Reducing Wire Lengths in the Layout of Cyclic Shifters
Peter-Michael SEIDEL Mark A. HILLEBRAND Thomas SCHURGER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2714-2721
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
cyclic shifterlayoutwire lengthwire delay
 Summary | Full Text:PDF

Fault-Tolerant Meshes with Efficient Layouts
Toshinori YAMADA Shuichi UENO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/25
Vol. E81-D  No. 1 ; pp. 56-65
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
meshesfault-tolerant graphsembeddingslayoutswire length
 Summary | Full Text:PDF