Keyword : wire delay


Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2619-2627
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
coarse-grained reconfigurable architecturedynamically reconfigurable processorhigh-level synthesisiterative synthesiswire delay
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Reducing Wire Lengths in the Layout of Cyclic Shifters
Peter-Michael SEIDEL Mark A. HILLEBRAND Thomas SCHURGER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2714-2721
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
cyclic shifterlayoutwire lengthwire delay
 Summary | Full Text:PDF

PCHECK: A Delay Analysis Tool for High Performance LSI Design
Yoshio MIKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2117-2122
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
delay analysiscritical pathdevice delaywire delayPCHECK
 Summary | Full Text:PDF