Keyword : way scaling


Way-Scaling to Reduce Power of Cache with Delay Variation
Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3576-3584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
leakagepower reductioncachewithin-die variationdelay variationway scaling
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