Keyword : video decoder

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
Jinjia ZHOU Dajiang ZHOU Xun HE Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/08/01
Vol. E93-A  No. 8 ; pp. 1425-1433
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: VLSI Design Technology and CAD
Keyword: 
motion vector derivation, DRAM bandwidth, ultra high resolution, video decoder, H.264/AVC, 
 Summary | Full Text:PDF(914.3KB)
VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
Jinhyun CHO Doowon LEE Sangyong YOON Sanggyu PARK Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/01/01
Vol. E92-A  No. 1 ; pp. 279-290
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SMPTE 421M-2006 VC-1, video decoder, transaction level modeling, design space exploration, 
 Summary | Full Text:PDF(2.8MB)
ULSI Realization of MPEG2 Realtime Video Encoder and Decoder--An Overview
Masahiko YOSHIMOTO Shin-ichi NAKAGAWA Tetsuya MATSUMURA Kazuya ISHIHARA Shin-ichi URAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1668-1681
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
video compression/decompression, video encoder, video decoder, MPEG2, video signal processor, 
 Summary | Full Text:PDF(1.1MB)
A 600 mW Single Chip MPEG2 Video Decoder
Kiyoshi MIURA Hideki KOYANAGI Hiroshi SUMIHIRO Seiichi EMOTO Nozomu OZAKI Toshiro ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1691-1696
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
MPEG2, video decoder, low power dual-port RAM, multiple-clock, asynchoronization, 
 Summary | Full Text:PDF(616.8KB)
An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
Shin-ichi URAMOTO Akihiko TAKABATAKE Takashi HASHIMOTO Jun TAKEDA Gen-ichi TANAKA Tsuyoshi YAMADA Yukio KODAMA Atsushi MAEDA Toshiaki SHIMADA Shun-ichi SEKIGUCHI Tokumichi MURAKAMI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1697-1708
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
image compression, video decoder, MPEG2, 
 Summary | Full Text:PDF(1.1MB)