Keyword : verification


A Toolset for Validation and Verification of Automotive Control Software Using Formal Patterns
Yunja CHOI Dongwoo KIM 
Publication:   
Publication Date: 2017/07/01
Vol. E100-D  No. 7 ; pp. 1526-1529
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
validationverificationOSEK/VDXpatterns
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Spoken Term Detection Using SVM-Based Classifier Trained with Pre-Indexed Keywords
Kentaro DOMOTO Takehito UTSURO Naoki SAWADA Hiromitsu NISHIZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/10/01
Vol. E99-D  No. 10 ; pp. 2528-2538
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Machine Learning for Spoken Language Processing)
Category: Spoken term detection
Keyword: 
decision processpre-indexingspoken term detectionsupport vector machineverification
 Summary | Full Text:PDF

Low Cost, High Performance of Coplanar Waveguide Fabricated by Screen Printing Technology
Masahiro HORIBE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/10/01
Vol. E99-C  No. 10 ; pp. 1094-1099
Type of Manuscript:  INVITED PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: 
Keyword: 
screen printing technologycoplanar waveguidescattering parameterson-wafer measurementsimpedance standard substrate (ISS)verification
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Verification of Flow Matching Functionality in the Forwarding Plane of OpenFlow Networks
Sachin SHARMA Wouter TAVERNIER Sahel SAHHAF Didier COLLE Mario PICKAVET Piet DEMEESTER 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/11/01
Vol. E98-B  No. 11 ; pp. 2190-2201
Type of Manuscript:  Special Section PAPER (Special Section on Network Systems for Virtualized Environment)
Category: 
Keyword: 
OpenFlowin-bandout-of-bandverification
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TESLA Source Authentication Protocol Verification Experiment in the Timed OTS/CafeOBJ Method: Experiences and Lessons Learned
Iakovos OURANOS Kazuhiro OGATA Petros STEFANEAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5 ; pp. 1160-1170
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal Verification
Keyword: 
source authenticationTESLA protocolCafeOBJverificationtimed OTSlessons learned
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A Verification-Aware Design Methodology for Thread Pipelining Parallelization
Guo-An JIAN Cheng-An CHIEN Peng-Sheng CHEN Jiun-In GUO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10 ; pp. 2505-2513
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
verification3D depth map generationpipelineparallel computingbehavior model
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Decidability of the Security against Inference Attacks Using a Functional Dependency on XML Databases
Kenji HASHIMOTO Hiroto KAWAI Yasunori ISHIHARA Toru FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/05/01
Vol. E95-D  No. 5 ; pp. 1365-1374
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Database Security
Keyword: 
XML databaseinference attacksecurityverificationfunctional dependency
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Workflows with Passbacks and Incremental Verification of Their Correctness
Osamu TAKAKI Izumi TAKEUTI Noriaki IZUMI Koiti HASIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4 ; pp. 989-1002
Type of Manuscript:  Special Section PAPER (Special Section on Knowledge-Based Software Engineering)
Category: 
Keyword: 
workflowverificationcorrectnesspassbackincremental verification
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Narrow Fingerprint Sensor Verification with Template Updating Technique
SangWoo SIN Ru ZHOU Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/01/01
Vol. E95-A  No. 1 ; pp. 346-353
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
fingerprintbiometricverificationtemplate updatingnarrow fingerprint sensor
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A Verification and Analysis Tool Set for Embedded System Design
Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2788-2793
Type of Manuscript:  INVITED PAPER (Special Section on Mathematical Systems Science and its Applications)
Category: 
Keyword: 
embedded systemsverification
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Towards Inferring Inter-Domain Routing Policies in ISP Networks
Wei LIANG Jingping BI Zhongcheng LI Yiting XIA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/11/01
Vol. E94-B  No. 11 ; pp. 3049-3056
Type of Manuscript:  PAPER
Category: Network Management/Operation
Keyword: 
BGProuting policyverificationinference
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A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform
Jeonghun KIM Suki KIM Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/09/01
Vol. E93-D  No. 9 ; pp. 2500-2508
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Bluetooth V2.0enhanced data rate (EDR)low-power architecturewireless SOCsub band codecplatform-based designverification
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Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8 ; pp. 1349-1358
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
STIstressmodelverificationenhancement
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HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
Liang-Bi CHEN Jiun-Cheng JU Chien-Chou WANG Ing-Jer HUANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2100-2108
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
AMBAdebuggingsystem-on-a-chip (SoC)protocol checkerverification
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Towards Reliable E-Government Systems with the OTS/CafeOBJ Method
Weiqiang KONG Kazuhiro OGATA Kokichi FUTATSUGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/05/01
Vol. E93-D  No. 5 ; pp. 974-984
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal Specification
Keyword: 
e-Government messaging frameworkformal methodsthe OTS/CafeOBJ methodfalsificationverification
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Feature Interaction Verification Using Unbounded Model Checking with Interpolation
Takafumi MATSUO Tatsuhiro TSUCHIYA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/06/01
Vol. E92-D  No. 6 ; pp. 1250-1259
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
unbounded model checkinginterpolationfeature interactionverification
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Probabilistic Model Checking of the One-Dimensional Ising Model
Toshifusa SEKIZAWA Tatsuhiro TSUCHIYA Koichi TAKAHASHI Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 1003-1011
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Model Checking
Keyword: 
verificationprobabilistic model checkingthe Ising modelDiscrete Time Markov Chain
 Summary | Full Text:PDF

Verification of the Security against Inference Attacks on XML Databases
Kenji HASHIMOTO Kimihide SAKANO Fumikazu TAKASUKA Yasunori ISHIHARA Toru FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 1022-1032
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Security
Keyword: 
XML databaseinference attacksecurityverification
 Summary | Full Text:PDF

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3793-3802
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum circuitverificationdecision diagram
 Summary | Full Text:PDF

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3539-3547
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
FPGA prototypingILPI/O pins constraintverificationtime-multiplexed I/O
 Summary | Full Text:PDF

On Backward-Style Anonymity Verification
Yoshinobu KAWABE Ken MANO Hideki SAKURADA Yasuyuki TSUKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9 ; pp. 2597-2606
Type of Manuscript:  PAPER
Category: Cryptography and Information Security
Keyword: 
formal methodsanonymitysoftware securityverificationtheorem-proving
 Summary | Full Text:PDF

A Specification Translation from Behavioral Specifications to Rewrite Specifications
Masaki NAKAMURA Weiqiang KONG Kazuhiro OGATA Kokichi FUTATSUGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/05/01
Vol. E91-D  No. 5 ; pp. 1492-1503
Type of Manuscript:  PAPER
Category: Fundamentals of Software and Theory of Programs
Keyword: 
specification translationverificationalgebraic specificationbehavioral specificationrewirte specificationCafeOBJMaude
 Summary | Full Text:PDF

An Adversary Model for Simulation-Based Anonymity Proof
Yoshinobu KAWABE Hideki SAKURADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1112-1120
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
formal methodsanonymitysoftware securityverificationtheorem-proving
 Summary | Full Text:PDF

An XQDD-Based Verification Method for Quantum Circuits
Shiou-An WANG Chin-Yung LU I-Ming TSAI Sy-Yen KUO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 584-594
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum computingquantum circuitsverificationdecision diagram
 Summary | Full Text:PDF

Instruction Based Synthesizable Testbench Architecture
Ho-Seok CHOI Hae-Wook CHOI Sin-Chong PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5 ; pp. 653-657
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
verificationtestbenchemulationinstruction
 Summary | Full Text:PDF

Accelerating Verification with Reusable Testbench
Jungbo SON Hae-Wook CHOI Sin-Chong PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/02/01
Vol. E89-D  No. 2 ; pp. 853-856
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
verificationtestbenchreuseAptixCelaro
 Summary | Full Text:PDF

Verifiable Oblivious Transfer Protocol
Narn-Yih LEE Chien-Chih WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2890-2892
Type of Manuscript:  LETTER
Category: Application Information Security
Keyword: 
oblivious transferverificationzero knowledgecryptographysame message attack
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Symbolic Reachability Analysis of Probabilistic Linear Hybrid Automata
Yosuke MUTSUDA Takaaki KATO Satoshi YAMANE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 2972-2981
Type of Manuscript:  Special Section PAPER (Special Section on Concurrent/Hybrid Systems: Theory and Applications)
Category: 
Keyword: 
verificationperformance evaluationformal specificationprobabilistic hybrid automatareachabilitysymbolic methods
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Policy Controlled System and Its Model Checking
Shigeta KUNINOBU Yoshiaki TAKATA Naoya NITTA Hiroyuki SEKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1685-1696
Type of Manuscript:  PAPER
Category: Application Information Security
Keyword: 
policy controlpolicy controlled systemverificationmodel checkingpushdown system
 Summary | Full Text:PDF

Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories
Jin-Fu LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3185-3192
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
system on chipembedded memoriesverificationsignal misplaced fault
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A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 630-636
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword: 
simulationtestVLSItesterverification
 Summary | Full Text:PDF

Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis
Hidefumi KUROKAWA Hiroyuki IKEGAMI Motohide OTSUBO Kiyoshi ASAO Kazuhisa KIRIGAYA Katsuya MISU Satoshi TAKAHASHI Tetsuji KAWATSU Kouji NITTA Hiroshi RYU Kazutoshi WAKABAYASHI Minoru TOMOBE Wataru TAKAHASHI Akira MUKOUYAMA Takashi TAKENAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4 ; pp. 787-798
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
C-based designbehavioral synthesisverificationdesign productivitymodel abstraction
 Summary | Full Text:PDF

Symbolic Model Checking of Deadlock Free Property of Task Control Architecture
Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1579-1586
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
verificationsymbolic model checkingdeadlockrobot control programconcurrent process
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Identification Algorithm Using a Matching Score Matrix
Takuji MAEDA Masahito MATSUSHITA Koichi SASAKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/07/01
Vol. E84-D  No. 7 ; pp. 819-824
Type of Manuscript:  Special Section PAPER (Special Issue on Biometric Person Authentication)
Category: 
Keyword: 
identificationverificationbiometricsfingerprintmatrixcorrelation
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High Level Analysis of Clock Regions in a C++ System Description
Luc RYNDERS Patrick SCHAUMONT Serge VERNALDE Ivo BOLSENS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2631-2632
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-level Synthesis
Keyword: 
clocking analysisC++ modelingverificationmodel of computation
 Summary | Full Text:PDF

A New Verification Method Using Virtual System States for Responsive Communication Protocols and Its Application to a Broadcasting Protocol
Shin'ichi NAGANO Yoshiaki KAKUDA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 596-604
Type of Manuscript:  Special Section PAPER (Special Section on Concurrent Systems Technology)
Category: 
Keyword: 
communication protocolresponsivenessverificationvirtual system statereachability analysis
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Refinement and Validation of Software Requirements Using Incremental Simulation
Kyo-Chul KANG Kwan W. LEE Ji-young LEE Jounghyun (Gerard) KIM Hye-jung KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/02/25
Vol. E81-D  No. 2 ; pp. 171-182
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
real-time systemsrequirements specificationrequirements analysisspecification executionstatechartvalidationverificationincremental development
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Time-Action Alternating Model for Timed Processes and Its Symbolic Verification of Bisimulation Equivalence
Akio NAKATA Teruo HIGASHINO Kenichi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Vol. E80-A  No. 2 ; pp. 400-406
Type of Manuscript:  PAPER
Category: Concurrent Systems
Keyword: 
timed bisimulation equivalenceverificationsymbolic bisimulationA-TSLTSmost general boolean
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On Verification of Token Self-Cleanness of Data-Flow Program Nets
Qi-Wei GE Kenji ONAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/06/25
Vol. E79-A  No. 6 ; pp. 812-817
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1995 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '95))
Category: 
Keyword: 
data-flow programprogram nettoken selfcleannessverification
 Summary | Full Text:PDF

A Flexible Verifier of Temporal Properties for LOTOS
Kaoru TAKAHASHI Yoshiaki TOKITA Takehisa TANAKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/01/25
Vol. E79-D  No. 1 ; pp. 8-21
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
specificationverificationprotocolLOTOSsoftware tool
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Verification and Refinement for System Requirements
Kukhwan SONG Atushi TOGASHI Norio SHIRATORI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/11/25
Vol. E78-A  No. 11 ; pp. 1468-1478
Type of Manuscript:  Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design)
Category: 
Keyword: 
system requirementformal specificationstate transitionPetri Netverificationrefinement
 Summary | Full Text:PDF

Practical Program Validation for State-Based Reactive Concurrent Systems--Harmonization of Simulation and Verification--
Naoshi UCHIHIRA Hideji KAWATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/11/25
Vol. E78-A  No. 11 ; pp. 1487-1497
Type of Manuscript:  Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design)
Category: 
Keyword: 
state transition systemreactive concurrent systemexhaustive simulationverificationstate space analysispartial order method
 Summary | Full Text:PDF

Hierarchical Analysis System for VLSI Power Supply Network
Takeshi YOSHITOME 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1659-1665
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
LSI layoutverificationpower supply networkvoltage drop
 Summary | Full Text:PDF

Critical Slice-Based Fault Localization for Any Type of Error
Takao SHIMOMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/06/25
Vol. E76-D  No. 6 ; pp. 656-667
Type of Manuscript:  PAPER
Category: Software Systems
Keyword: 
algorithmic debuggingerrorsfailuresfaultsslicesverification
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On the Specification for VLSI Systolic Arrays
Fuyau LIN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4 ; pp. 496-506
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
formal specificationZsystolic architecturesverification
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A Spoken Dialog System with Verification and Clarification Queries
Mikio YAMAMOTO Satoshi KOBAYASHI Yuji MORIYA Seiichi NAKAGAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/01/25
Vol. E76-D  No. 1 ; pp. 84-94
Type of Manuscript:  Special Section PAPER (Special Issue on Speech and Discourse Processing in Dialogue Systems)
Category: 
Keyword: 
natural language processingspeech recognitiondialog systemverificationclarification
 Summary | Full Text:PDF

Verification of Register Transfer Level (RTL) Designs
Alberto Palacios PAWLOVSKY Sachio NAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 785-791
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
fault analysistestingverificationhardware description languagesregular expressionsdirected graphs
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A Method of Composing Communication Protocols with Priority Service
Masahiro HIGUCHI Hiroyuki SEKI Tadao KASAMI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/10/25
Vol. E75-B  No. 10 ; pp. 1032-1042
Type of Manuscript:  Special Section PAPER (Special Issue on Communication Software Technologies)
Category: 
Keyword: 
communication protocolcommunicating sequential machinessafety propertyverificationreachability analysis
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Verification of Switching Software by Knowledge Processing Technology
Mitsuaki KAKEMIZU Yasuo IWAMI Yoshiharu SATO Shimmi HATTORI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/10/25
Vol. E75-B  No. 10 ; pp. 1008-1014
Type of Manuscript:  Special Section PAPER (Special Issue on Communication Software Technologies)
Category: 
Keyword: 
verificationknowledge baseobject-orientedsimulationswitching software
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Formal Specification and Verification of ISDN Services in LOTOS
Keiichirou YAMANO Dusan JOKANOVIC Tsuyoshi ANDO Masataka OHTA Kaoru TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/08/25
Vol. E75-B  No. 8 ; pp. 715-722
Type of Manuscript:  Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS))
Category: 
Keyword: 
LOTOSspecificationverificationswitching software
 Summary | Full Text:PDF