Keyword : variable ordering


An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD
Tomonori IZUMI Shin'ichi KOUYAMA Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
reconfigurable systemdesign technologylogic synthesisvariable orderinglook-up table
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A Genetic Algorithm for the Minimization of OPKFDDs
Migyoung JUNG Gueesang LEE Sungju PARK Rolf DRECHSLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2943-2945
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
OBDDOPKFDDGAvariable orderingdecomposition
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Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
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The Complexity of the Optimal Variable Ordering Problems of a Shared Binary Decision Diagram
Seiichiro TANI Kiyoharu HAMAGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4 ; pp. 271-281
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
ordered binary decision diagramvariable orderingoptimal linear arrangementNP-completeBoolean function
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Minimum-Width Method of Variable Ordering for Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 392-399
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagramsboolean functionlogic synthesisvariable ordering
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