Keyword : triple modular redundancy


An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 741-750
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architecturereliabilitytriple modular redundancyimmediate terminationerror-critical period
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Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2530-2539
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
triple modular redundancylow energyMIPsimulated annealingschedule exploration
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A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 454-462
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft errorsingle event upsettriple modular redundancyreliabilitysimulated annealing
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