Keyword : transition delay fault

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Akihiro TOMITA Xiaoqing WEN Yasuo SATO Seiji KAJIHARA Kohei MIYASE Stefan HOLST Patrick GIRARD Mohammad TEHRANIPOOR Laung-Terng WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10 ; pp. 2706-2718
Type of Manuscript:  PAPER
Category: Dependable Computing
at-speed scan-based logic BISTcapture power safetymaskingIR-droptransition delay faultlong sensitized path
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