Keyword : top-down design and bottom-up verification methodology

New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data
Yuichi TANJI Masaya SUZUKI Takayuki WATANABE Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/02/01
Vol. E88-A  No. 2 ; pp. 524-532
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
top-down design and bottom-up verification methodologyorthogonal least-squares methodVerilog-AMSVerilog-Asampled datamatrix rational approximation
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