IEICE Trans

Keyword : timing verification

Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion Kazuhiro NAKAMURA Shinji MARUOKA Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2600-2607 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: timing verification, maximum delay analysis, multi-cycle paths, propositional satisfiability,
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Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2515-2520 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Optimization Keyword: timing verification, maximum delay analysis, multiple clock operation, false path,
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Prciseness of Discrete Time Verification Shinji KIMURA Shunsuke TSUBOTA Hiromasa HANEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 ; pp. 1755-1759 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: timing verification, discrete time analysis, timing simulation, unit time selection,
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Hierarchical Timing Analyzer for Multiple Phase Clocked Designs Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/12/25 Vol. E75-A No. 12 ; pp. 1732-1735 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Fall Conference) Category: Keyword: timing analysis, timing verification, static timing analysis, hierarchical timing analysis, synchronous design, CAD,
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Timing Verification of Logic Circuits with Combined Delay Model Shinji KIMURA Shigemi KASHIMA Hiromasa HANEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1230-1238 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: timing verification, computer aided design, logic simulation,
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Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1247-1254 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic circuits, timing verification, symbolic simulation, Boolean function manipulation,
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