Keyword : timing optimization

Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3151-3158
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesis, sequential circuit, timing optimization, level-sensitive latch, formal verification, 
 Summary | Full Text:PDF
Robust Performance Optimization Using Padding Nodes and Separator Sets
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2739-2745
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
timing optimization, separator set, network flow algorithm, 
 Summary | Full Text:PDF
LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 331-336
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
gate sizing, timing optimization, power consumption, linear programming, 
 Summary | Full Text:PDF
Timing Optimization of Multi-Level Networks Using Boolean Relations
Yuji KUKIMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3 ; pp. 362-369
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
timing optimization, logic synthesis, logic optimization, Boolean relations, Boolean unification, 
 Summary | Full Text:PDF