Keyword : timing constraints


Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System
Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2208-2219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dual-vddmin-cutvoltage assignmentlow powertiming constraints
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Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11 ; pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verificationfailure analysistimed circuitstiming constraints
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Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelismlow power designfault tolerancetiming constraintsspeculative execution
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An Efficient Timing-Driven Global Routing Method for Standard Cell Layout
Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1410-1418
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
standard cell layoutglobal routingtiming constraintsslack distribution0-1 integer linear programming
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