Keyword : timing constraint


Timing-Constrained Flexibility-Driven Routing Tree Construction
Jin-Tai YAN Yen-Hsiang CHEN Chia-Fang LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1360-1368
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
global routingrouting flexibilitySteiner treetiming constraint
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An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints
Jun'ichiro MINAMI Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2569-2576
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
circuit partitioningiterative improvementFM methodtiming constraintpath-cut number
 Summary | Full Text:PDF

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layoutglobal routingpin assignmenttiming constraintsimulated evolution
 Summary | Full Text:PDF