IEICE Trans

Keyword : timing analysis

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration Cheng-Yu HAN Yu-Ching LI Hao-Tien KAN James Chien-Mo LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 ; pp. 2320-2327 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: IR-drop, power-supply-noise, timing analysis, testing,
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Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis Takashi ENAMI Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2261-2271 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power distribution network, decoupling capacitance, timing analysis, statistical static timing analysis, decap insertion, wire sizing,
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Stress Probability Computation for Estimating NBTI-Induced Delay Degradation Hiroaki KONOURA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2545-2553 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: NBTI, stress probability, timing analysis,
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Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/10/01 Vol. E94-A No. 10 ; pp. 1948-1953 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, Flip-Flop, setup time, hold time, timing analysis,
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Gate Delay Estimation in STA under Dynamic Power Supply Noise Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2447-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power supply noise, gate delay, timing analysis,
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Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits Shiho HAGIWARA Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 1031-1038 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: device parameter variation, MTCMOS, timing analysis, Monte-Carlo simulation,
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New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects Tae Il BAE Jin Wook KIM Young Hwan KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3488-3496 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: crosstalk, gate model, delay calculation, timing analysis,
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An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis Masanori IMAI Takashi SATO Noriaki NAKAYAMA Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 ; pp. 957-964 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, STA, Monte Carlo STA, timing analysis, ranking,
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Timing Analysis Considering Temporal Supply Voltage Fluctuation Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 ; pp. 655-660 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Verification and Timing Analysis Keyword: timing analysis, dynamic power supply noise,
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Timing Analysis Considering Spatial Power/Ground Level Variation Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2661-2668 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: timing analysis, power supply noise, gate delay model, power/ground level variation,
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An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs Kenji SHIMAZAKI Makoto NAGATA Mitsuya FUKAZAWA Shingo MIYAHARA Masaaki HIRATA Kazuhiro SATOH Hiroyuki TSUJIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 ; pp. 1535-1543 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: power-supply noise, ground noise, noise detector, dynamic IR drop, timing analysis,
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Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay Zhangcai HUANG Atsushi KUROKAWA Yun YANG Hong YU Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 ; pp. 840-846 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: CMOS inverter, overshooting effect, deep submicron, timing analysis,
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Efficient False Aggressors Pruning with Functional Correlation Hyungwoo LEE Juho KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3159-3165 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: signal integrity, false aggressor, crosstalk, timing analysis,
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Routing Methodology for Minimizing Crosstalk in SoC Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/09/01 Vol. E86-A No. 9 ; pp. 2347-2356 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: SoC, signal integrity, crosstalk, interconnect, timing analysis,
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Hierarchical Timing Analyzer for Multiple Phase Clocked Designs Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/12/25 Vol. E75-A No. 12 ; pp. 1732-1735 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Fall Conference) Category: Keyword: timing analysis, timing verification, static timing analysis, hierarchical timing analysis, synchronous design, CAD,
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