Keyword : timing analysis


Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration
Cheng-Yu HAN Yu-Ching LI Hao-Tien KAN James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2320-2327
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
IR-droppower-supply-noisetiming analysistesting
 Summary | Full Text:PDF

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis
Takashi ENAMI Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2261-2271
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power distribution networkdecoupling capacitancetiming analysisstatistical static timing analysisdecap insertionwire sizing
 Summary | Full Text:PDF

Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
Hiroaki KONOURA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2545-2553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
NBTIstress probabilitytiming analysis
 Summary | Full Text:PDF

Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
Takaaki OKUMURA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10 ; pp. 1948-1953
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
power supply noiseFlip-Flopsetup timehold timetiming analysis
 Summary | Full Text:PDF

Gate Delay Estimation in STA under Dynamic Power Supply Noise
Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2447-2455
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
power supply noisegate delaytiming analysis
 Summary | Full Text:PDF

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits
Shiho HAGIWARA Takashi SATO Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1031-1038
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
device parameter variationMTCMOStiming analysisMonte-Carlo simulation
 Summary | Full Text:PDF

New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
Tae Il BAE Jin Wook KIM Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3488-3496
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
crosstalkgate modeldelay calculationtiming analysis
 Summary | Full Text:PDF

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
Masanori IMAI Takashi SATO Noriaki NAKAYAMA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 957-964
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTASTAMonte Carlo STAtiming analysisranking
 Summary | Full Text:PDF

Timing Analysis Considering Temporal Supply Voltage Fluctuation
Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 655-660
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Verification and Timing Analysis
Keyword: 
timing analysisdynamic power supply noise
 Summary | Full Text:PDF

Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2661-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
timing analysispower supply noisegate delay modelpower/ground level variation
 Summary | Full Text:PDF

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs
Kenji SHIMAZAKI Makoto NAGATA Mitsuya FUKAZAWA Shingo MIYAHARA Masaaki HIRATA Kazuhiro SATOH Hiroyuki TSUJIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1535-1543
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
power-supply noiseground noisenoise detectordynamic IR droptiming analysis
 Summary | Full Text:PDF

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay
Zhangcai HUANG Atsushi KUROKAWA Yun YANG Hong YU Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 840-846
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
CMOS inverterovershooting effectdeep submicrontiming analysis
 Summary | Full Text:PDF

Efficient False Aggressors Pruning with Functional Correlation
Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3159-3165
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
signal integrityfalse aggressorcrosstalktiming analysis
 Summary | Full Text:PDF

Routing Methodology for Minimizing Crosstalk in SoC
Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/09/01
Vol. E86-A  No. 9 ; pp. 2347-2356
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCsignal integritycrosstalkinterconnecttiming analysis
 Summary | Full Text:PDF

Hierarchical Timing Analyzer for Multiple Phase Clocked Designs
Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1732-1735
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
timing analysistiming verificationstatic timing analysishierarchical timing analysissynchronous designCAD
 Summary | Full Text:PDF