Keyword : through silicon via

Signal Propagation Delay Model in Vertically Stacked Chips
Nanako NIIOKA Masayuki WATANABE Masa-aki FUKASE Masashi IMAI Atsushi KUROKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2614-2624
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
3-D IC, delay, through silicon via, sensitivity analysis, 
 Summary | Full Text:PDF(2.5MB)
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking
Satoshi TAKAYA Hiroaki IKEDA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6 ; pp. 557-565
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
wide I/O bus, through silicon via, signal integrity, power integrity, 
 Summary | Full Text:PDF(2.7MB)