Keyword : threshold operation


Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 948-955
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
logic value conversion (LVC)floating-gate MOS transistorthreshold operationsingle-transistor cellfully parallel template matching
 Summary | Full Text:PDF(570.7KB)

Safety Control of Power Press by Using Fail-Safe Multiple-Valued Logic
Masayoshi SAKAI Masakazu KATO Koichi FUTSUHARA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 577-585
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Fail-Safe/Fault Tolerant
Keyword: 
fault tolerancemultiple-valued logicfail-safethreshold operationpower press control
 Summary | Full Text:PDF(752.5KB)

LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations
Masakazu KATO Masayoshi SAKAI Koji JINKAWA Koichi FUTSUHARA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 419-427
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
fault tolerancemultiple-valued logicfail-safethreshold operationthreshold operation device
 Summary | Full Text:PDF(808.4KB)