IEICE Trans

Keyword : testing

Spectrum-Based Fault Localization Using Fault Triggering Model to Refine Fault Ranking List Yong WANG Zhiqiu HUANG Rongcun WANG Qiao YU
Publication: Publication Date: 2018/10/01 Vol. E101-D No. 10 ; pp. 2436-2446 Type of Manuscript: PAPER Category: Software Engineering Keyword: fault localization, software debugging, testing,
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Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration Cheng-Yu HAN Yu-Ching LI Hao-Tien KAN James Chien-Mo LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 ; pp. 2320-2327 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: IR-drop, power-supply-noise, timing analysis, testing,
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Design for Testability That Reduces Linearity Testing Time of SAR ADCs Tomohiko OGAWA Haruo KOBAYASHI Satoshi UEMORI Yohei TAN Satoshi ITO Nobukazu TAKAI Takahiro J. YAMAGUCHI Kiichi NIITSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 ; pp. 1061-1064 Type of Manuscript: BRIEF PAPER Category: Keyword: SAR ADC, testing, DC linearity, design for testability, built-in self-test,
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Modeling, Verification and Testing of Web Applications Using Model Checker Kei HOMMA Satoru IZUMI Kaoru TAKAHASHI Atsushi TOGASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/05/01 Vol. E94-D No. 5 ; pp. 989-999 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Software Development Methodology Keyword: Web application, modeling, testing, automata, model checking, Spin,
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An Efficient Fault Syndromes Simulator for SRAM Memories Wan Zuha WAN HASAN Izhal ABD HALIN Roslina MOHD SIDEK Masuri OTHMAN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/05/01 Vol. E92-C No. 5 ; pp. 639-646 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: testing, diagnosis, coupling faults, stuck-at faults March test algorithm, built-in self-test (BIST), built-in self-diagnosis (BISD), automated march-based test algorithm, SRAM,
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Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits Yukiya MIURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 ; pp. 564-570 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Fault Detection Keyword: bridging faults, CMOS synchronous sequential circuits, fault analysis, testing,
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Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults Jin-Fu LI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 ; pp. 601-608 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Memory Testing Keyword: content addressable memories, testing, diagnosis, march test,
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Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification Eunjung OH Jeong-Gun LEE Dong-Ik LEE Ho-Yong CHOI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/06/01 Vol. E84-A No. 6 ; pp. 1506-1514 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000)) Category: Keyword: ATPG, SI asynchronous circuits, signal transition graph, testing,
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Fast Testable Design for SRAM-Based FPGAs Abderrahim DOUMAR Toshiaki OHMAMEUDA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/05/25 Vol. E83-D No. 5 ; pp. 1116-1127 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: field programmable gate array (FPGA), testing, design for testing, shifting configurations,
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Fault Behavior and Change in Internal Condition of Mixed-Signal Circuits Yukiya MIURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/04/25 Vol. E83-D No. 4 ; pp. 943-945 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: CMOS mixed-signal circuits, fault analysis, MOS transistors, operation regions, testing,
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OTA-C Based BIST Structure for Analog Circuits Cheng-Chung HSU Wu-Shiung FENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/04/25 Vol. E83-A No. 4 ; pp. 771-773 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: built-in self-test (BIST), operational transconductance amplifier (OTA), analog circuit, fault diagnosis, testing,
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Electro-Optic Testing Technology for High-Speed LSIs Tadao NAGATSUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/25 Vol. E79-C No. 4 ; pp. 482-488 Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: electro-optics, Pockels effect, sampling, pulse laser, testing,
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Applying OSI Systems Management Standards to Remotely Controlled Virtual Path Testing in ATM Networks Satoru OHTA Nobuo FUJII
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1993/03/25 Vol. E76-B No. 3 ; pp. 280-290 Type of Manuscript: Special Section PAPER (Special Issue on Broadband ISDN --Application, Networking and Management--) Category: Keyword: communication systems and transmission equipment, ATM, testing, network management, OSI systems management, managed object,
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Verification of Register Transfer Level (RTL) Designs Alberto Palacios PAWLOVSKY Sachio NAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/25 Vol. E75-D No. 6 ; pp. 785-791 Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems) Category: Keyword: fault analysis, testing, verification, hardware description languages, regular expressions, directed graphs,
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