IEICE Trans

Keyword : testing and verification

An Analysis of the Economics of the VLSI Development Including Test Cost Koji NAKAMAE Homare SAKAMOTO Hiromu FUJIOKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/04/25 Vol. E77-A No. 4 ; pp. 698-705 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: testing and verification, economics of VLSI development, test cost, VLSI development cycle, EB tester, FIB reconstruction, fault modeling,
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The Enhancement of Electromigration Lifetime under High Frequency Pulsed Conditions Kazunori HIRAOKA Kazumitsu YASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/01/25 Vol. E77-A No. 1 ; pp. 195-203 Type of Manuscript: Special Section PAPER (Special Section on Reliability) Category: Reliability Testing Keyword: fault analysis, testing and verification, reliability, availability and vulnerability,
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Enhanced Unique Sensitization for Efficient Test Generation Yusuke MATSUNAGA Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1114-1120 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Test Keyword: computer hardware and disign, testing and verification,
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Analysis of Engine States and Automobile Features Based on Time-Dependent Spectral Characteristics Yumi TAKIZAWA Shinichi SATO Keisuke ODA Atsushi FUKASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/11/25 Vol. E75-A No. 11 ; pp. 1524-1532 Type of Manuscript: Special Section PAPER (Special Section on Acoustic System Modeling and Signal Processing) Category: Keyword: digital signal processing, modeling and simulation, acoustics, signals and waves, fault analysis, testing and verification,
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