Keyword : testability

Scan-Based Attack on AES through Round Registers and Its Countermeasure
Youhua SHI Nozomu TOGAWA Masao YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
scan-based side channel attack, crypto implementation, security, testability, 
 Summary | Full Text:PDF
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
Ryuta NARA Kei SATOH Masao YANAGISAWA Tatsuo OHTSUKI Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2481-2489
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
scan-based side-channel attack, scan path, testability, cryptosystem, RSA, security, 
 Summary | Full Text:PDF
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
Ryuta NARA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3229-3237
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
scan-based attack, side-channel attack, scan chain, testability, security, cryptography, AES, 
 Summary | Full Text:PDF
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9 ; pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing, 
 Summary | Full Text:PDF
New Three-Level Boolean Expression Based on EXOR Gates
Ryoji ISHIKAWA Takashi HIRAYAMA Goro KODA Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/05/01
Vol. E87-D  No. 5 ; pp. 1214-1222
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
EXOR gates, three-level logic, pseudoproduct, compact design, testability, 
 Summary | Full Text:PDF
Novel Techniques for Improving Testability Analysis
Yin-He SU Ching-Hwa CHENG Shih-Chieh CHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2901-2912
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
testability, controllability, observability, TAIR, COP, 
 Summary | Full Text:PDF
A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement
Taewhan KIM Ki-Seok CHUNG C. L. LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6 ; pp. 1070-1081
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesis, testability, scheduling, 
 Summary | Full Text:PDF
High-Level Synthesis for Weakly Testable Data Paths
Michiko INOUE Kenji NODA Takeshi HIGASHIMURA Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 645-653
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Test Synthesis
Keyword: 
high-level synthesis, testability, sequential ATPG, non-scan design, 
 Summary | Full Text:PDF
On Acceleration of Test Points Selection for Scan-Based BIST
Michinobu NAKAO Kazumi HATAYAMA Isao HIGASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 668-674
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Built-in Self-Test
Keyword: 
test points, BIST, optimization, testability, 
 Summary | Full Text:PDF