Keyword : test


A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
Hong-Ming SHIEH Jin-Fu LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10 ; pp. 2428-2434
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
system-on-chiptestcompressionmulti-code compressiondecompression
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Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI
Satoshi SHIGEMATSU Hiroki MORIMURA Toshishige SHIMAMURA Takahiro HATANO Namiko IKEDA Yukio OKAZAKI Katsuyuki MACHIDA Mamoru NAKANISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1892-1899
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
testpixel parallelsensorfingerprint identificationsingle chiphigh-functional deviceMEMS
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A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 630-636
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword: 
simulationtestVLSItesterverification
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Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2527-2529
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
asynchronouspipelineevent logiclatchtest
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On Testing of Josephson Logic Circuits Composed of the 4JL Gates
Teruhiko YAMADA Tsuyoshi SASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 749-752
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Diagnosis of VLSI)
Category: 
Keyword: 
Josephson logic circuittestdefect coverage
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A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs
Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 582-589
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMtestredundancy
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A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 38-43
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
crosstalk faultfault simulationsequential circuittest
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Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit
Shigeharu TESHIMA Naoya CHUJO Ryuta TERASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 853-860
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
testfault-simulationmixed-signal circuitfault-model
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A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
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