Keyword : test synthesis


Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 861-867
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
retiminglogic synthesisredundancy removaltest synthesis
 Summary | Full Text:PDF

Test Synthesis from Behavioral Description Based on Data Transfer Analysis
Mitsuteru YUKISHITA Kiyoshi OGURI Tsukasa KAWAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 248-251
Type of Manuscript:  Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
computer hardware and designhardware description languagetest synthesisSFL
 Summary | Full Text:PDF