Keyword : test structure


Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2669-2675
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorhardened designvariabilitytest structureshift register
 Summary | Full Text:PDF(3.1MB)

Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns
Takashi NASUNO Yoshihisa MATSUBARA Hiromasa KOBAYASHI Akiyuki MINAMI Eiichi SODA Hiroshi TSUDA Koichiro TSUJITA Wataru WAKAMIYA Nobuyoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 796-803
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
test structure65 nm-nodevia chainOBIRCHfailure analysis
 Summary | Full Text:PDF(2.6MB)

Measuring Contact Resistance of a Poly-Silicon Plug on a Lightly Doped Single-Diffusion Region in DRAM Cells
Naoki KASAI Hiroki KOGA Yoshihiro TAKAISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5 ; pp. 1146-1150
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
test structurecontact resistancepoly-silicon plugDRAM cell
 Summary | Full Text:PDF(943.2KB)

A New Test Structure for Precise Location Measurement of Hot-Carrier-Induced Photoemission Peak in Subquarter-Micron MOSFETs
Toshihiro MATSUDA Mari FUNADA Takashi OHZONE Etsumasa KAMEDA Shinji ODANAKA Kyoji TAMASHITA Norio KOIKE Ken-ichiro TATSUUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5 ; pp. 1125-1133
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
test structureMOSFEThot carrierphotoemission
 Summary | Full Text:PDF(1.8MB)

Advanced Characterization Method for Sub-Micron DRAM Cell Transistors
Ikuo KURACHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 618-623
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
DRAMcell transistorstest structureparameter extractionparasitic resistance
 Summary | Full Text:PDF(715.6KB)

Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI
Tetsuhisa MIDO Hiroshi ITO Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 570-575
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
test structurecapacitance matrixVLSI interconnectionshift registersnon-overlap clock signalsub-femto-farad measurement
 Summary | Full Text:PDF(651.6KB)

Characterisation of Offset Lithographic Films Using Microelectronic Test Structures
Anthony J. WALTON J. Tom M. STEVENSON Leslie I. HAWORTH Martin FALLON Peter S. A. EVANS Blue J. RAMSEY David HARRISON 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 576-581
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
microelectronicstest structureoffset lithographylinewidth
 Summary | Full Text:PDF(780.7KB)

Effects of Field Edge Steps on Electrical Gate Linewidth Measurements
Naoki KASAI Ichiro YAMAMOTO Koji URABE Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 152-157
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
Keyword: 
test structureMOSFETlinewidthfield step
 Summary | Full Text:PDF(798KB)

Reliability Evaluation of Thin Gate Oxide Using a Flat Capacitor Test Structure
Masafumi KATSUMATA Jun-ichi MITSUHASHI Kiyoteru KOBAYASHI Yoji MASHIKO Hiroshi KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 206-210
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Reliability Analysis
Keyword: 
test structurevery low-level currentatto amperesmeasurement technique
 Summary | Full Text:PDF(388.8KB)

Test Structure for the Evaluation of Si Substrates
Yoshiko YOSHIDA Mikihiro KIMURA Morihiko KUME Hidekazu YAMAMOTO Hiroshi KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 192-197
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: SOI & Material Characterization
Keyword: 
silicon substratecrystal defectTDDBtest structure
 Summary | Full Text:PDF(781.5KB)