Keyword : test pattern generation


SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faultsadjacent linestest pattern generationcoupling capacitanceSAT-based ATPG
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Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
Hiroyuki YOTSUYANAGI Masayuki YAMAMOTO Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1 ; pp. 10-16
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
BIST-aided scan testscan chain orderingtest data reductioncompatible flip-flopstest pattern generation
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A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
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Efficient Test Generation Using Redundancy Identification
Sangyoon HAN Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/09/25
Vol. E83-D  No. 9 ; pp. 1814-1815
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
test pattern generationredundant faults
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The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs
Tokumi YOKOHIRA Toshimi SHIMIZU Hiroyuki MICHINISHI Yuji SUGIYAMA Takuji OKAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 874-881
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-testexhaustive testingtest pattern generationminimum test setdependence matrix
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MINT--An Exact Algorithm for Finding Minimum Test Set--
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1652-1658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test pattern generationminimum test setbinary decision diagramminimum set covering problem
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REDUCT: A Redundant Fault Identification Algorithm Using Circuit Reduction Techniques
Miyako TANDAI Takao SHINSHA Takao NISHIDA Kaoru MORIWAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 776-790
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
hardware and designalgorithmdiagnosistest pattern generationredundant fault
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Minimum Test Set for Locally Exhaustive Testing of Multiple Output Combinational Circuits
Hiroyuki MICHINISHI Tokumi YOKOHIRA Takuji OKAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 791-799
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
built-in-self-testpseudoexhaustive testingverification testinglocally exhaustive testingtest pattern generation
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