Keyword : test cost reduction


Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage
Masayuki ARAI Kazuhiko IWASAKI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1488-1495
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
weighted fault coveragecritical areatest cost reductiontest pattern reductionbridge faultopen fault
 Summary | Full Text:PDF

Low-Cost IP Core Test Using Tri-Template-Based Codes
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 288-295
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityIP core testingtest cost reductiontest data compression
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Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3 ; pp. 1157-1164
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
concurrent testingSOC testingtest cost reductiontest data compression
 Summary | Full Text:PDF

X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1662-1670
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SOC testingtest cost reductiontest data compressionunknown statetest diagnosis
 Summary | Full Text:PDF

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5 ; pp. 984-992
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
hybrid pattern BISTcore testingtest cost reductionFPGA corereconfigurable system-on-a-chip
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Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1498-1505
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
at-speed testBISRembedded DRAMtest cost reduction
 Summary | Full Text:PDF