Keyword : test compaction

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3 ; pp. 533-540
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defects, test compaction, test application time, test data volume, on-chip delay measurement, 
 Summary | Full Text:PDF
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution
Hiroshi YAMAZAKI Motohiro WAKAZONO Toshinori HOSOKAWA Masayoshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1994-2002
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
X-bit, don't care identification, X-bit distribution, test compaction, 
 Summary | Full Text:PDF
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme
Kohei MIYASE Xiaoqing WEN Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA Patrick GIRARD Laung-Terng WANG Mohammad TEHRANIPOOR 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1 ; pp. 2-9
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
power supply noise, test relaxation, X-filling, clock-gating, test compaction, 
 Summary | Full Text:PDF
A Fault Model for Multiple-Valued PLA's and Its Equivalences
Yasunori NAGATA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9 ; pp. 1527-1534
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
equivalences of faults, fault model, multiple-valued logic, programmable logic array, test compaction, 
 Summary | Full Text:PDF