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| Keyword : technology mapping
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Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A
No. 7 ;
pp. 1374-1380
Type of Manuscript:
Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category:
Keyword:
logic synthesis, technology mapping, FPGA, SAT, | | | Summary | Full Text:PDF | |
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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3268-3275
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
FPGA, technology mapping, cut enumeration, | | | Summary | Full Text:PDF | |
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A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs
Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A
No. 3 ;
pp. 473-482
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
technology mapping, logic-block, lookup table, logic depth, | | | Summary | Full Text:PDF | |
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Path Mapping: Delay Estimation for Technology Independent Synthesis
Yutaka TAMIYA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1782-1788
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
technology independent synthesis, technology mapping, delay estimation, | | | Summary | Full Text:PDF | |
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Technology Mapping for FPGAs with Composite Logic Block Architectures
Hsien-Ho CHUANG C. Bernard SHUNG | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D
No. 10 ;
pp. 1396-1404
Type of Manuscript:
Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword:
technology mapping, FPGA, subject graph, pattern graph, | | | Summary | Full Text:PDF | |
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A
No. 3 ;
pp. 321-329
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
FPGA, technology mapping, layout, path delay, performance optimization, | | | Summary | Full Text:PDF | |
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