Keyword : systolic array


High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Masamitsu TANAKA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 703-709
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
digital arithmeticdigit-serial processinghardware algorithmrapid single-flux-quantum logicsigned-digit representationsystolic array
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Low Complexity Systolic Array Structure for Extended QRD-RLS Equalizer
Ji-Hye SHIN Young-Beom JANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2407-2414
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
equalizerextended QRD-RLSsystolic arrayCORDIC
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A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 465-478
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
low powermotion estimationH.264systolic arrayMBAFFSRAM
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Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation
Yoshiaki YOKOYAMA Minseok KIM Hiroyuki ARAI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/04/01
Vol. E91-B  No. 4 ; pp. 1068-1075
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
systolic arrayQR decompositionRLSCORDICFPGA
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A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
Seungbeom LEE Hanho LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/03/01
Vol. E91-A  No. 3 ; pp. 830-835
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Reed-Solomon (RS) codesdegree-computationlessmodified Eulclideansystolic array
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A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3623-3633
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationH.264SIMDsystolic array
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Merging of Systolic Messy Arrays Based on Data Flows
Makio ISHIHARA Hironori KIDA Minoru TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 639-643
Type of Manuscript:  LETTER
Category: General Fundamentals and Boundaries
Keyword: 
mergingsystolic messy arraysystolic arraydata flow
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Systolic OMF-RAKE: Linear Interference Canceller Utilizing Systolic Array for Mobile Communications
Thet Htun KHINE Kazuhiko FUKAWA Hiroshi SUZUKI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/05/01
Vol. E88-B  No. 5 ; pp. 2128-2135
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
DS-CDMAblind linear-interference-cancellerRAKEQR-RLSsystolic array
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Reliable Data Routing for Spatial-Temporal TMR Multiprocessor Systems
Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/12/01
Vol. E84-D  No. 12 ; pp. 1790-1800
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
systolic arrayfault toleranceon-line error correctionroutingnetwork architecture
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Efficient Telescopic Search Motion-Estimation Architecture Based on Data-Flow Optimization
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 390-398
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion estimationtelescopic searchsystolic arraylatencylow-power
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Systolic Implementations of Modified Gaussian Eliminations for the Decoding of Reed-Solomon Codes
Chih-Wei LIU Li-Lien LIN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/10/25
Vol. E82-A  No. 10 ; pp. 2251-2258
Type of Manuscript:  PAPER
Category: Information Theory and Coding Theory
Keyword: 
systolic arrayGaussian eliminationRS codeHong-Vetterli algorithmFIABerlekamp-Massey algorithm
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Design Optimization of VLSI Array Processor Architecture for Window Image Processing
Dongju LI Li JIANG Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/08/25
Vol. E82-A  No. 8 ; pp. 1475-1484
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
image processingarray processorwindow operationsystolic array
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A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
Mineo KANEKO Hiroyuki MIYAUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/12/25
Vol. E79-D  No. 12 ; pp. 1676-1689
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
VLSI array processorsystolic arrayfault tolerancecommunication linkdependence graph
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Memory Sharing Processor Array (MSPA) Architecture
Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2086-2096
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesissystolic array
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A Highly Parallel Systolic Tridiagonal Solver
Takashi NARITOMI Hirotomo ASO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9 ; pp. 1241-1247
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
scientific computingparallel processingparallel algorithmtridiagonal linear systemsystolic array
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A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video
Shin-ichi URAMOTO Akihiko TAKABATAKE Mitsuyoshi SUZUKI Hiroki SAKURAI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1930-1936
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processors
Keyword: 
image compressionmotion estimationsystolic array
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Mapping QR Decomposition on Parallel Computers: A Study Case for Radar Applications
Antonio d'ACIERNO Michele CECCARELLI Alfonso FARINA Alfredo PETROSINO Luca TIMMONERI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/10/25
Vol. E77-B  No. 10 ; pp. 1264-1271
Type of Manuscript:  PAPER
Category: Electronic and Radio Applications
Keyword: 
Radarsidelobe cancelerQR decompositionparallel processingsystolic arrayMIMD computersSIMD computers
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Application of DBF Technique to Radar Systems
Shin'ichi TAKEYA Mitsuyoshi SHINONAGA Yoshitaka SASAKI Hiroshi MIYAUCHI Masanori MATSUMURA Tasuku MOROOKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/02/25
Vol. E77-B  No. 2 ; pp. 256-260
Type of Manuscript:  PAPER
Category: Electronic and Radio Applications
Keyword: 
digital beamformingsystolic arrayadaptive arraymulti-beamforming
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Reconfiguration Algorithm for Modular Redundant Linear Array
Chang CHEN An FENG Yoshiaki KAKUDA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/02/25
Vol. E76-D  No. 2 ; pp. 210-218
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault tolerant computingsystolic arrayN-modular redundancyreconfigurable modular redundant linear arrayreconfiguration algorithm
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