Keyword : systolic array architecture

Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations
Yang SONG Zhenyu LIU Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 108-117
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Image Technology)
motion estimation (ME)partial distortion sorting (PDS)systolic array architecture
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