Keyword : system-on-chip testing


Scheduling Power-Constrained Tests through the SoC Functional Bus
Fawnizu Azmadi HUSSIN Tomokazu YONEDA Alex ORAILOLU Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 736-746
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
functional busfunctional TAMpower-constrainedpacket-based schedulingsystem-on-chip testing
 Summary | Full Text:PDF(810.6KB)

Preemptive System-on-Chip Test Scheduling
Erik LARSSON Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 620-629
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanism designpreemptive schedulingsystem-on-chip testing
 Summary | Full Text:PDF(3.2MB)