Keyword : system-level design


Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Ittetsu TANIGUCHI Junya KAIDA Takuji HIEDA Yuko HARA-AZUMI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11 ; pp. 2827-2834
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
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Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Junya KAIDA Yuko HARA-AZUMI Takuji HIEDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/10/01
Vol. E96-D  No. 10 ; pp. 2268-2271
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
 Summary | Full Text:PDF

Physical Architecture and Model-Based Evaluation of Electric Power System with Multiple Homes
Yoshihiko SUSUKI Ryoya KAZAOKA Takashi HIKIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/08/01
Vol. E96-A  No. 8 ; pp. 1703-1711
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
power systemarchitecturemodelbifurcationuncertaintysystem-level design
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Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2509-2516
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
system-level designhardware sharingdesign space explorationMPSoC
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A Practical Method for System-Level Bus Architecture Validation
Kazuyoshi TAKEMURA Masanobu MIZUNO Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2439-2445
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
system-level designbus architecture validationbus-cycle-accuratebehavioral modelinterface model
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