IEICE Trans

Keyword : system on chip

Hardware-Based Principal Component Analysis for Hybrid Neural Network Trained by Particle Swarm Optimization on a Chip Tuan Linh DANG Yukinobu HOSHINO
Publication: Publication Date: 2019/10/01 Vol. E102-A No. 10 ; pp. 1374-1382 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: neural network, principal component analysis, particle swarm optimization, hardware-based, system on chip,
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An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs Yosuke OGASAWARA Ryuichi FUJIMOTO Tsuneo SUZUKI Kenichi SAMI
Publication: Publication Date: 2017/06/01 Vol. E100-C No. 6 ; pp. 529-538 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: spur, clock spur, SCCG, SSCG, BLE, sensitivity recovery, clock generation, system on chip,
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60 GHz Millimeter-Wave CMOS Integrated On-Chip Open Loop Resonator Bandpass Filters on Patterned Ground Shields Ramesh K. POKHAREL Xin LIU Dayang A.A. MAT Ruibing DONG Haruichi KANAYA Keiji YOSHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/02/01 Vol. E96-C No. 2 ; pp. 270-276 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: millimeter-wave, on-chip band pass filter, pattern ground shields, folded structure, system on chip,
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Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Ki-Yong AHN Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 ; pp. 2318-2325 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: system on chip, low power design, partitioning, integer linear programming,
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A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/10/01 Vol. E88-C No. 10 ; pp. 2020-2027 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: embedded memory, DRAM, voltage margin, low voltage, system on chip,
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Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories Jin-Fu LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3185-3192 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: system on chip, embedded memories, verification, signal misplaced fault,
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A Low Power Embedded DRAM Macro for Battery-Operated LSIs Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 2991-3000 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power Optimization Keyword: embedded memory, DRAM, low power, system on chip,
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A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 ; pp. 1697-1708 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: embedded DRAM, system on chip, 3-D graphics concurrent operation,
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Large Scale Embedded DRAM Technology Akira YAMAZAKI Tadato YAMAGATA Yutaka ARITA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 750-758 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: DRAM Keyword: embedded DRAM, system on chip, system LSI,
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Embedded System Cost Optimization via Data Path Width Adjustment Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Akihiko INOUE Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/25 Vol. E80-D No. 10 ; pp. 974-981 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High Level Synthesis Keyword: embedded systems, system on chip, CPU, memory,
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Integration of a Power Supply for System-on-Chip Satoshi MATSUMOTO Masato MINO Toshiaki YACHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 ; pp. 276-282 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration) Category: Keyword: power supply, system on chip, power IC, SOI, thin-film magnetic device,
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