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| Keyword : synthesis
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A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG Chien-Jyh LIU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12 ;
pp. 3109-3115
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
low-power, architecture, VLSI design, FSM, gating, synthesis, | | | Summary | Full Text:PDF(755KB) | |
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A Cell Synthesis Method for Salicide Process Using Assignment Graph
Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2577-2583
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword:
cell, layout, synthesis, salicide, assignment graph, | | | Summary | Full Text:PDF(581.5KB) | |
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Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems
Rakefet KOL Ran GINOSAR Goel SAMUEL | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D
No. 3 ;
pp. 308-314
Type of Manuscript:
Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Specification Description
Keyword:
asynchronous logic design, statechart, validation, synthesis, | | | Summary | Full Text:PDF(572.8KB) | |
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