Keyword : synchronous DRAM


A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application
Hoi-Jun YOO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/08/25
Vol. E80-C  No. 8 ; pp. 1126-1128
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
low voltageself-timed CMOS logicsynchronous DRAM
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A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme
Hisashi IWAMOTO Naoya WATANABE Akira YAMAZAKI Seiji SAWADA Yasumitsu MURAI Yasuhiro KONISHI Hiroshi ITOH Masaki KUMANOYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1328-1333
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
synchronous DRAMSDRAMhigh speed DRAMmultiple-register
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1303-1315
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMmemory bottleneckdata bandwidthlatencysynchronous DRAMpipeline architecturedata prefetchingcache DRAMfast copybackRambus interfaceRambus DRAMprotocol packetPLL
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Small-Amplitude Bus Drive and Signal Transmission Technology for High-Speed Memory-CPU Bus Systems
Tatsuo KOIZUMI Seiichi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1582-1588
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
bus transmissionI/O interfacesmall amplitudesynchronous DRAM
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