Keyword : superscalar


An Energy Efficient Instruction Window for Scalable Processor Architecture
Min CHOI Seungryoul MAENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1427-1436
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
instruction windowsuperscalarlow-power microarchitecturereorder bufferissue queue
 Summary | Full Text:PDF

SIMD ISA Extensions: Power Efficiency on Multimedia on a Superscalar Processor
Julien SEBOT Nathalie DRACH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 297-303
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
multimediaSIMDsuperscalarlow power
 Summary | Full Text:PDF

Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
Jin-Hyuk YANG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/10/25
Vol. E82-D  No. 10 ; pp. 1338-1343
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
superscalarinstruction fetchtrace cache
 Summary | Full Text:PDF

Invariant-Free Formal Verification of Pipelined and Superscalar Controls by Behavior-Covering and Partial Unfolding
Toru SHONAI Tsuguo SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2 ; pp. 376-388
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
formal verificationprocessorpipelinesuperscalar
 Summary | Full Text:PDF

The Effect of Instruction Window on the Performance of Superscalar Processors
Yong-Hyeon PYUN Choung-Shik PARK Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1036-1044
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Systems and Control
Keyword: 
superscalarinstruction windowin-order issueout-of-order issueinstruction issue rate
 Summary | Full Text:PDF

Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO Chikako NAKANISHI Hirohisa MACHIDA Tetsuya HARA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1080-1093
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
superscalarVLIWspeculative execution
 Summary | Full Text:PDF