Keyword : superscalar processor


Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4 ; pp. 822-837
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister filemultibanking
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FXA: Executing Instructions in Front-End for Energy Efficiency
Ryota SHIOYA Ryo TAKAMI Masahiro GOSHIMA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4 ; pp. 1092-1107
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorhybrid in-order/out-of-order coreenergy efficiency
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Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
Ryota SHIOYA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/03/01
Vol. E99-D  No. 3 ; pp. 630-640
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister renamingtrace cacheenergy efficiency
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Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2 ; pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelismpower consumption
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MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism
Yuya KORA Kyohei YAMAGUCHI Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12 ; pp. 3110-3123
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelism
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Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification
Kyohei YAMAGUCHI Yuya KORA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/09/01
Vol. E95-D  No. 9 ; pp. 2235-2246
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processorissue queuedelaycomplexity
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Analytical Models and Performance Analyses of Instruction Fetch on Superscalar Processors
Sun-Mo KIM Jung-Woo LEE Soo-Haeng LEE Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6 ; pp. 1442-1453
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
instruction cacheinstruction fetchanalytical modelsuperscalar processor
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A Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Motokazu OZAWA Masashi IMAI Yoichiro UENO Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 229-237
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
asynchronoussuperscalar processorcascade ALUfine grain pipeline
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Reorder Buffer Structure with Shelter Buffer for Out-of-Order Issue Superscalar Processors
Mun-Suek CHANG Choung-Shik PARK Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1091-1099
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
superscalar processorout-of-order issuereorder bufferstagnationshelter buffer
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System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method
Hak-Jun KIM Sun-Mo KIM Sang-Bang CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6 ; pp. 927-938
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
Category: 
Keyword: 
superscalar processorinstruction-level parallelismin-order issueout-of-order issueinstruction windowreorder bufferqueuing model
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A 1000 MIPS Superscalar Processor and Its Fault Tolerant Design
Alberto Palacios PAWLOVSKY Makoto HANAWA Osamu NISHII Tadahiko NISHIMUKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1212-1222
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: RISC Technologies
Keyword: 
superscalar processormultiprocessor systemBiCMOS devicesfault-toleranceconcurrent fault detection
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