IEICE Trans

Keyword : supercomputer

Set-to-Set Disjoint Paths Routing in Torus-Connected Cycles Antoine BOSSARD Keiichi KANEKO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/11/01 Vol. E99-D No. 11 ; pp. 2821-2823 Type of Manuscript: LETTER Category: Dependable Computing Keyword: torus, many-to-many, parallel system, fault-tolerance, dependable, supercomputer,
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Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/03/01 Vol. E91-C No. 3 ; pp. 350-355 Type of Manuscript: INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics) Category: Keyword: superconductor, rapid single-flux-quantum circuit, reconfigurable data-path, high-performance computing, supercomputer,
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The Development of the Earth Simulator Shinichi HABATA Mitsuo YOKOKAWA Shigemune KITAWAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 ; pp. 1947-1954 Type of Manuscript: INVITED PAPER (Special Issue on Development of Advanced Computer Systems) Category: Keyword: supercomputer, HPC (high performance computing), parallel processing, shared memory, vector processor, crossbar network,
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Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer Tadayuki SAKAKIBARA Katsuyoshi KITAI Tadaaki ISOBE Shigeko YAZAWA Teruo TANAKA Yoshiko TAMAKI Yasuhiro INAGAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/25 Vol. E80-D No. 9 ; pp. 925-932 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Computer Architecture Keyword: supercomputer, vector processor, TCMP, arbitrate, interprocessor memory access conflict,
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Scalable Parallel Memory Architecture with a Skew Scheme Tadayuki SAKAKIBARA Katsuyoshi KITAI Tadaaki ISOBE Shigeko YAZAWA Teruo TANAKA Yasuhiro INAGAMI Yoshiko TAMAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/25 Vol. E80-D No. 9 ; pp. 933-941 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Computer Architecture Keyword: supercomputer, vector processor, interleaved parallel memory, skew scheme, memory access conflict, permanent-concentration, transient-concentration,
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