IEICE Trans

Keyword : stuck-at fault

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2563-2570 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: asynchronous on-chip interconnect, CHAIN, stuck-at fault, test scheduling, integer linear programming,
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On Fault Testing for Reversible Circuits Satoshi TAYU Shigeru ITO Shuichi UENO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/12/01 Vol. E91-D No. 12 ; pp. 2770-2775 Type of Manuscript: PAPER Category: Complexity Theory Keyword: 3-SAT, CNOT gate, complete test set, fault testing, NP-complete, reversible circuit, stuck-at fault, test vector,
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On Finding Don't Cares in Test Sequences for Sequential Circuits Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 ; pp. 2748-2755 Type of Manuscript: PAPER Category: Dependable Computing Keyword: test generation, don't care value, sequential circuit, stuck-at fault,
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Generation of Test Sequences with Low Power Dissipation for Sequential Circuits Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 ; pp. 530-536 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Test Generation and Compaction Keyword: LSI testing, sequential circuit, test generation, low power dissipation, stuck-at fault,
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A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG Hideyuki ICHIHARA Tomoo INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3072-3078 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: test generation, acyclic sequential circuits, stuck-at fault, partial scan, multiple fault,
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A Learning Algorithm with Activation Function Manipulation for Fault Tolerant Neural Networks Naotake KAMIURA Yasuyuki TANIGUCHI Yutaka HATA Nobuyuki MATSUI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/07/01 Vol. E84-D No. 7 ; pp. 899-905 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: feedforward neural network, backpropagation algorithm, stuck-at fault, sigmoid activation function,
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RAM BIST Jacob SAVIR
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/01/01 Vol. E84-C No. 1 ; pp. 102-107 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: memory test, stuck-at fault, coupled-cell faults, pattern-sensitive faults, test length, confidence level, Markov chain,
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Complete Diagnosis Patterns for Wiring Interconnects Sungju PARK Gueesang LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/04/25 Vol. E81-A No. 4 ; pp. 672-676 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: boundary scan, shorted nets fault, stuck-at fault, fault detection, fault diagnosis, interconnect test,
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The Effect of CMOS VLSI IDDq Measurement on Defect Level Junichi HIRASE Masanori HAMADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-D No. 7 ; pp. 839-844 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: IDDq test, CMOS VLSI, fault coverage, defect level, toggle rate, stuck-at fault, design for testability,
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Test Sequence Generation for Sequential Circuits with Distinguishing Sequences Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 ; pp. 1730-1737 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: distinguishing sequence, stuck-at fault, sequential circuit, test sequence generation, design rechnique,
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