Keyword : structured ASIC


Via Programmable Structured ASIC Architecture “VPEX3” and CAD Design System
Ryohei HORI Taisuke UEOKA Taku OTANI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2182-2190
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
via programmable logic devicestructured ASICexclusive-ORmiddle-volume production
 Summary | Full Text:PDF

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation
Ryohei HORI Tatsuya KITAMORI Taisuke UEOKA Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9 ; pp. 1518-1528
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
via programmable logic devicestructured ASICmiddle volume production
 Summary | Full Text:PDF

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing
Akihiro NAKAMURA Masahide KAWARASAKI Kouta ISHIBASHI Masaya YOSHIKAWA Takeshi FUJINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 509-516
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
via-programmable logicelectron-beam direct writinglow volume productionexclusive ORstructured ASIClook-up table
 Summary | Full Text:PDF