Keyword : statistical timing analysis


Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers
Xingbao ZHOU Fan YANG Hai ZHOU Min GONG Hengliang ZHU Ye ZHANG Xuan ZENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/11/01
Vol. E97-A  No. 11 ; pp. 2227-2235
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Post-Silicon Tunable bufferstatistical timing analysisstochastic collocationsparse grid
 Summary | Full Text:PDF(1.7MB)

Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation
Shinyu NINOMIYA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2441-2446
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical timing analysismanufacturing variability
 Summary | Full Text:PDF(1.1MB)

Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Takashi ENAMI Shinyu NINOMIYA Ken-ichi SHINKAI Shinya ABE Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2399-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical timing analysisclock jittersetup verificationstructural correlationpower supply noise
 Summary | Full Text:PDF(964.2KB)

A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together
Shingo TAKAHASHI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/03/01
Vol. E92-A  No. 3 ; pp. 900-911
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
statistical timing analysisGaussian mixture modeldelay distributionslew distributionvariability
 Summary | Full Text:PDF(656.7KB)

Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model
Yi WANG Xuan ZENG Jun TAO Hengliang ZHU Wei CAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3465-3473
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
statistical timing analysisadaptive stochastic collocation methodprocess variations
 Summary | Full Text:PDF(418.3KB)

An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis
Shuji TSUKIYAMA Masahiko TOMITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 535-543
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
correlation coefficientinterconnect delayElmore delaystatistical timing analysisGaussian distribution
 Summary | Full Text:PDF(563KB)

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation
Jing-Jia LIOU Li-C. WANG Angela KRSTIĆ Kwang-Ting (Tim) CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3038-3048
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
delay testcritical pathstatistical timing analysis
 Summary | Full Text:PDF(624.3KB)

Statistical Gate-Delay Modeling with Intra-Gate Variability
Kenichi OKADA Kento YAMAOKA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 2914-2922
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Parasitics and Noise
Keyword: 
intra-chip variabilitystatistical timing analysisintra-gate variabilitymanufacturing fluctuation
 Summary | Full Text:PDF(677.1KB)

Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence
Kenichi OKADA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4 ; pp. 746-751
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
intra-chip variabilitystatistical timing analysismanufacturing fluctuation
 Summary | Full Text:PDF(384.7KB)

Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2799-2802
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimizationdelay increasestatistical timing analysisdelay uncertaintytransistor sizing
 Summary | Full Text:PDF(297.5KB)