IEICE Trans

Keyword : statistical timing analysis

Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers Xingbao ZHOU Fan YANG Hai ZHOU Min GONG Hengliang ZHU Ye ZHANG Xuan ZENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/11/01 Vol. E97-A No. 11 ; pp. 2227-2235 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Post-Silicon Tunable buffer, statistical timing analysis, stochastic collocation, sparse grid,
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Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation Shinyu NINOMIYA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2441-2446 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical timing analysis, manufacturing variability,
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Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation Takashi ENAMI Shinyu NINOMIYA Ken-ichi SHINKAI Shinya ABE Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2399-2408 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical timing analysis, clock jitter, setup verification, structural correlation, power supply noise,
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A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together Shingo TAKAHASHI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/03/01 Vol. E92-A No. 3 ; pp. 900-911 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: statistical timing analysis, Gaussian mixture model, delay distribution, slew distribution, variability,
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Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model Yi WANG Xuan ZENG Jun TAO Hengliang ZHU Wei CAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3465-3473 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical timing analysis, adaptive stochastic collocation method, process variations,
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An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis Shuji TSUKIYAMA Masahiko TOMITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 ; pp. 535-543 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: correlation coefficient, interconnect delay, Elmore delay, statistical timing analysis, Gaussian distribution,
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Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation Jing-Jia LIOU Li-C. WANG Angela KRSTIĆ Kwang-Ting (Tim) CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3038-3048 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: delay test, critical path, statistical timing analysis,
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Statistical Gate-Delay Modeling with Intra-Gate Variability Kenichi OKADA Kento YAMAOKA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 2914-2922 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: intra-chip variability, statistical timing analysis, intra-gate variability, manufacturing fluctuation,
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Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence Kenichi OKADA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 ; pp. 746-751 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: intra-chip variability, statistical timing analysis, manufacturing fluctuation,
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Increase in Delay Uncertainty by Performance Optimization Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2799-2802 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: performance optimization, delay increase, statistical timing analysis, delay uncertainty, transistor sizing,
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