Keyword : static timing analysis


Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability
Song BIAN Michihiro SHINTANI Masayuki HIROMOTO Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1400-1409
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
NBTIreliabilitystatic timing analysistiming characterizationaging-aware timing library
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A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model
Takahiro KAWAGUCHI Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2556-2564
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
single-flux-quantum circuitstatic timing analysisformal verification
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A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/05/01
Vol. E94-A  No. 5 ; pp. 1201-1209
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
static timing analysisgate delayeffective capacitancenon-iterative
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Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10 ; pp. 2531-2539
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
static timing analysisgate delayeffective capacitanceThevenin model
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Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits
Naoaki OHKUBO Kimiyoshi USAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3482-3490
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
MTCMOSselective-MTstatic timing analysisleakage powerdelay modeling
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
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Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG Atsushi KUROKAWA Jun PAN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3367-3374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
static timing analysisgate slewCMOS invertereffective capacitanceinterconnect loads
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A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/10/01
Vol. E88-A  No. 10 ; pp. 2562-2569
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
static timing analysisgate delayCMOS invertereffective capacitanceinterconnect loads
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An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays
Shuji TSUKIYAMA Masakazu TANAKA Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2746-2754
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
static timing analysisstatistical approachcorrelationnormal distributionCMOS combinatorial circuits
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A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2558-2568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
statistical static timing analysisstatic timing analysisgate resizingtransistor sizingperformance optimization
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Hierarchical Timing Analyzer for Multiple Phase Clocked Designs
Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1732-1735
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
timing analysistiming verificationstatic timing analysishierarchical timing analysissynchronous designCAD
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