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Keyword : standard cell

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology Tian WANG Xiaoxin CUI Kai LIAO Nan LIAO Xiaole CUI Dunshan YU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 ; pp. 974-983 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: VLSI, FinFET, standard cell, stacking, back biasing,
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A 0.0055mm² 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI Dongsheng YANG Tomohiro UENO Wei DENG Yuki TERASHIMA Kengo NAKATA Aravind Tharayil NARAYANAN Rui WU Kenichi OKADA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 ; pp. 632-640 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: AD-PLL, synthesizable, stochastic TDC, standard cell, automatic place-and-route,
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A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation Toshiyuki YAMAGISHI Tatsuo SHIOZAWA Koji HORISAKI Hiroyuki HARA Yasuo UNEKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 ; pp. 894-902 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on chip, monitor, digital, process variability, standard cell, area efficiency,
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Low-Leakage and Low-Power Implementation of High-Speed Logic Gates Tsung-Yi WU Liang-Ying LU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 ; pp. 401-408 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: dual value logic, leakage current, pass-transistor logic gate, standard cell, transmission gate,
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Manufacturability-Aware Design of Standard Cells Hirokazu MUTA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2682-2690 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: manufacturability, variability, DFM, ACLV, standard cell, OPC, RET,
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Navigating Register Placement for Low Power Clock Network Design Yongqiang LU Chin-Ngai SZE Xianlong HONG Qiang ZHOU Yici CAI Liang HUANG Jiang HU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3405-3411 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan and Placement Keyword: clock network, standard cell, quadratic placement, prescribed skew,
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Design of Small RSFQ Microprocessor Based on Cell-Based Top-Down Design Methodology Futabako MATSUZAKI Kenichi YODA Junichi KOSHIYAMA Kei MOTOORI Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 659-664 Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: SFQ, BDD, superconducting circuit, microprocessor, standard cell,
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Analog Standard Cells for A-D and D-A Converters with Δ-Σ Modulators Takao KANEKO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/02/25 Vol. E83-A No. 2 ; pp. 252-260 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog layout, mixed analog-digital LSI, standard cell, Δ-Σ type A-D converter, Δ-Σ type D-A converter,
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A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs Keiichi KOIKE Kenji KAWAI Akira ONOZAWA Yuichiro TAKEI Yoshiji KOBAYASHI Haruhiko ICHINO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 ; pp. 1578-1585 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: Si bipolar, ECL, standard cell, CAD, SDH,
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An Asynchronous Cell Library for Self-Timed System Designs Yuk-Wah PANG Wing-yun SIT Chiu-sing CHOY Cheong-fat CHAN Wai-kuen CHAM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/03/25 Vol. E80-D No. 3 ; pp. 296-307 Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design) Category: Design Keyword: self-timed logic, asynchronous design, standard cell, VLSI,
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1.4 GHz Natural Air-Cooling GaAs Standard Cell LSIs for 10 Gbit/s Optical Communication Systems Yasunori OGAWA Kuniichi IKEMURA Shouhei SEKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/25 Vol. E79-C No. 4 ; pp. 489-495 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: GaAs, DCFL, SDH, standard cell, natural air-cooling,
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High Speed GaAs Digital Integrated Circuits Masahiro AKIYAMA Seiji NISHI Yasushi KAWAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/09/25 Vol. E78-C No. 9 ; pp. 1165-1170 Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices) Category: Keyword: GaAs digital IC, DCFL, SBFL, high speed, low power, self-alignment process, recessed gate process, circuit design, standard cell,
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Cell Designer: An Automatic Placement and Routing Tool for the Mixed Design of Macro and Standard Cells Young Seok BAEK Byoung Yoon CHEON Kyung Sik KIM Hyun Chan LEE Chul Dong LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/02/25 Vol. E75-A No. 2 ; pp. 224-232 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: VLSI/CAD, layout, placement, routing, macro cell, standard cell,
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