Keyword : standard cell design


Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization
Daijoon HYUN Younggwang JUNG Youngsoo SHIN 
Publication:   
Publication Date: 2019/12/01
Vol. E102-A  No. 12 ; pp. 1711-1719
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
stitch-induced viastandard cell designmask assignmentdetailed placementcell mapping
 Summary | Full Text:PDF

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation
Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2499-2507
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
standard cell designlow power circuit designnear threshold operationPN ratio optimization
 Summary | Full Text:PDF