Keyword : speedup of lock up time


PLL Frequency Synthesizer with Multi-Phase Detector
Yasuaki SUMI Kouichi SYOUBU Shigeki OBOTE Yutaka FUKUI Yoshio ITOH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 431-435
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
PLL frequency synthesizermulti-phase detectorspeedup of lock up time
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