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Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
Takayuki OBATA Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12 ;
pp. 3585-3595
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
high level synthesis, RT datapath, skew, wiring delay, scheduling, | | | Summary | Full Text:PDF | |
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A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Matsuaki TERADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C
No. 10 ;
pp. 1957-1963
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword:
Ethernet, VSR, backplane, skew, FEC, Fire codes, | | | Summary | Full Text:PDF | |
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C
No. 7 ;
pp. 1334-1340
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, | | | Summary | Full Text:PDF | |
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Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays
Midori TAKANO Fumihiro MINAMI Naohito KOJIMA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D
No. 10 ;
pp. 1405-1409
Type of Manuscript:
Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword:
clock routing, delay, skew, embedded array, | | | Summary | Full Text:PDF | |
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